Semiconductor package interconnect and power connection by metallized structures on package body

ABSTRACT

A method includes providing a lead frame including a die pad and a plurality of leads, providing a first semiconductor die that includes a first load terminal disposed on a main surface, providing a second semiconductor die that includes a plurality of I/O terminals disposed on a main surface, mounting the first and second semiconductor dies on the lead frame such that the main surfaces of the first and second semiconductor dies face away from the die pad, forming an encapsulant body of mold compound that encapsulates the first and second semiconductor dies, forming a plurality of conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals to a first group of the leads, and forming a metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.

TECHNICAL FIELD

The instant application relates to semiconductor devices, and inparticular relates to methods of forming semiconductor packages andcorresponding semiconductor package configurations.

BACKGROUND

High-voltage semiconductor devices such as MOSFETs (metal oxidesemiconductor field effect transistors), IGBTs (insulated gate bipolartransistors), diodes, etc., are commonly packaged in a moldedsemiconductor package that includes several leads protruding out anencapsulant body. These types of semiconductor packages are commonlyused in high power applications such as automotive, power transmission,HVAC, etc. Product performance requirements for high voltageapplications, such as low electrical resistance, low parasiticinductance, low parasitic capacitive coupling, etc. demand innovativesolutions. In particular, conventional interconnect techniques forelectrically connecting semiconductor dies to one another and/or topackage leads are ill-equipped to meet modern performance requirementswith a small package footprint. For instance, although the electricalresistance of bond wires can be favorably improved by increasing thediameter of the wires, this creates practical challenges in the assemblyprocess and increases the size of the package.

Thus, there is a need for an improved low parasitic package forsemiconductor devices.

SUMMARY

A method of forming a packaged semiconductor device is disclosed.According to an embodiment, the method comprises providing a lead framecomprising a die pad and a plurality of leads, providing a firstsemiconductor die that comprises a first load terminal disposed on amain surface of the first semiconductor die, providing a secondsemiconductor die that comprises a plurality of I/O terminals disposedon a main surface of the second semiconductor die, mounting the firstand second semiconductor dies on the lead frame such that the mainsurfaces of the first and second semiconductor dies each face away fromthe die pad, forming an encapsulant body of electrically insulating moldcompound that encapsulates the first and second semiconductor dies,forming a plurality of conductive tracks on an upper surface of theencapsulant body that electrically connect at least some of the I/Oterminals from the second semiconductor die to a first group of theleads, and forming a metal pad on the upper surface of the encapsulantbody that electrically connects the first load terminal to a secondlead.

Separately or in combination, the encapsulant body is formed to exposeinterior surface portions of the leads at the upper surface of theencapsulant body, wherein the conductive tracks are formed to contactthe interior surface portions of the leads from the first group of theleads, and wherein the metal pad is formed to contact the interiorsurface portion of the second lead.

Separately or in combination, the encapsulant body is formed to comprisea depression in the upper surface of the encapsulant body, and theexposed interior surface portions of the leads protrude out from a firstsidewall of the depression.

Separately or in combination, the method further comprises formingvertical interconnect elements on the I/O terminals of the secondsemiconductor die before forming the encapsulant body, wherein theencapsulant body is formed to expose upper ends of the verticalinterconnect elements that are disposed on the I/O terminals at theupper surface of the encapsulant body, and wherein the conductive tracksare formed to contact the exposed upper ends of the verticalinterconnect elements that are disposed on the I/O terminals.

Separately or in combination, forming either one of the plurality ofconductive tracks and the metal pad comprises any one or more of laserassisted metal deposition, inkjet metal printing, electroplating, andelectroless plating.

Separately or in combination, the method further comprises formingvertical interconnect elements on the first load terminal of the firstsemiconductor die before forming encapsulant body, and wherein theencapsulant body is formed to expose upper ends of the verticalinterconnect elements on the first load terminal at the upper surface ofthe encapsulant body.

Separately or in combination, the metal pad is formed on the uppersurface of the encapsulant body so as to contact the exposed upper endsof the vertical interconnect elements on the first load terminal.

Separately or in combination, the method further comprises forming anopening in the upper surface of the encapsulant body that exposes thefirst load terminal of the first semiconductor die, and wherein formingthe opening comprises using the exposed upper ends of the verticalinterconnect elements on the first load terminal to identify a locationof the first load terminal underneath the encapsulant body.

Separately or in combination, the method further comprises forming aribbon on the first load terminal of the first semiconductor die beforeforming encapsulant body, wherein the encapsulant body is formed toexpose apex points of the ribbon at the upper surface of the encapsulantbody, and wherein the metal pad is formed on the exposed apex points ofthe ribbon

Separately or in combination, the method further comprises forming asolder mask over the conductive tracks.

Separately or in combination, the method further comprises forming alayer of electrically insulating and thermally conductive material thatcovers the metal pad.

Separately or in combination, the encapsulant body is formed to directlyexpose the first load terminal and the I/O terminals at the firstsurface of the encapsulant body.

Separately or in combination, the first semiconductor die is a powertransistor die that comprises a gate terminal disposed on the mainsurface of the first semiconductor die, the second semiconductor die isa logic die, and the method further comprises forming a secondconductive track on the upper surface of the encapsulant body thatelectrically connects one of the I/O terminals from the secondsemiconductor die to the gate terminal of the first semiconductor die.

Separately or in combination, the first semiconductor die comprises asecond load terminal that is disposed on a rear surface of the firstsemiconductor die, wherein the second load terminal of the firstsemiconductor die faces and electrically connects with the die pad.

According to another embodiment, the method comprises providing a leadframe comprising a die pad and a plurality of leads, providing a firstsemiconductor die that comprises a first load terminal and a pluralityof I/O terminals disposed on a main surface of the first semiconductordie, providing a second semiconductor die that comprises a first loadterminal and a gate terminal disposed on a main surface of the secondsemiconductor die, mounting the first semiconductor die directly on thelead frame such that the main surface of the first semiconductor diefaces away from the lead frame, mounting the second semiconductor die onthe first semiconductor die such that the main surface of the secondsemiconductor die faces away from the lead frame, forming an encapsulantbody of electrically insulating mold compound that encapsulates thefirst and second semiconductor dies, forming a plurality of firstconductive tracks on an upper surface of the encapsulant body thatelectrically connect at least some of the I/O terminals from the firstsemiconductor die to a first group of the leads, forming a secondconductive track on the upper surface of the encapsulant body thatelectrically connects one of the I/O terminals from the firstsemiconductor die to the gate terminal of the second semiconductor die,forming a first metal pad on the upper surface of the encapsulant bodythat electrically connects the first load terminal of the firstsemiconductor die to a second lead, and forming a second metal pad onthe upper surface of the encapsulant body that electrically connects thefirst load terminal of the second semiconductor die to a third lead.

Separately or in combination, the first semiconductor die comprises apower transistor device block and a logic block monolithicallyintegrated in the first semiconductor die, wherein the second transistordie comprises a power transistor device, wherein the power transistordevice block of the first semiconductor die and the power transistordevice of the second semiconductor die form a half-bridge circuit, andwherein the logic block of the first semiconductor die forms a drivercircuit that is configured to control a switching operation of thehalf-bridge circuit.

Separately or in combination, the method further comprises providing athird semiconductor die that comprises a first load terminal and aplurality of I/O terminals disposed on a main surface of the thirdsemiconductor die, providing a fourth semiconductor die that comprises afirst load terminal and a gate terminal disposed on a main surface ofthe fourth semiconductor die, mounting the third semiconductor diedirectly on the lead frame such that the main surface of the thirdsemiconductor die faces away from the lead frame, and mounting thefourth semiconductor die on the third semiconductor die such that themain surface of the fourth semiconductor die faces away from the leadframe, wherein the third semiconductor die comprises a power transistordevice block and a logic block monolithically integrated in the thirdsemiconductor die, wherein the fourth transistor die comprises a powertransistor device, wherein the power transistor device block of thethird semiconductor die and the power transistor device of the fourthsemiconductor die form a second half-bridge circuit, and wherein thelogic block of the third semiconductor die forms a driver circuit thatis configured to control a switching operation of the second half-bridgecircuit.

A packaged semiconductor device is disclosed. According to anembodiment, the packaged semiconductor device comprises a lead framecomprising a die pad and a plurality of leads, a first semiconductor diethat comprises a first load terminal disposed on a main surface of thefirst semiconductor die that faces away from the die pad, a secondsemiconductor die that comprises a plurality of I/O terminals disposedon a main surface of the second semiconductor die that faces away fromthe die pad, an encapsulant body of electrically insulating moldcompound that encapsulates the first and second semiconductor dies, aplurality of conductive tracks that are formed on an upper surface ofthe encapsulant body and electrically connect at least some of the I/Oterminals from the second semiconductor die to a first group the leads,and a metal pad formed on the upper surface of the encapsulant body thatelectrically connects the first load terminal to a second lead.

Separately or in combination, interior surface portions of the leads areexposed at the upper surface of the encapsulant body, and wherein themetal pad and the conductive tracks contact the exposed interior surfaceportions of the leads.

Separately or in combination, the encapsulant body comprises adepression in the upper surface of the encapsulant body, and wherein theexposed interior surface portions of the leads protrude out from a firstouter sidewall of the depression.

Separately or in combination, the depression is spaced apart from anouter edge side of the encapsulant body by a thicker portion of the ofthe encapsulant body, and wherein upper surfaces of the leads arecovered by encapsulant material in the thicker portion.

Separately or in combination, the depression comprises a second sidewallthat is opposite from the first sidewall and a bottom surface, andwherein the metal pad completely fills a region between the first andsecond sidewalls of the depression.

Separately or in combination, the first semiconductor die is a powertransistor die that comprises a gate terminal disposed on the mainsurface of the first semiconductor die, the second semiconductor die isa logic die, and wherein the semiconductor package further comprises asecond plurality of conductive tracks on the upper surface of theencapsulant body that electrically connect at least one of the I/Oterminals from the second semiconductor die to the gate terminal of thesecond semiconductor die.

Separately or in combination, the first semiconductor die is mounted ontop of the second semiconductor die, and wherein the secondsemiconductor die is mounted directly on the die pad.

BRIEF DESCRIPTION OF THE DRAWINGS

The elements of the drawings are not necessarily to scale relative toeach other. Like reference numerals designate corresponding similarparts. The features of the various illustrated embodiments can becombined unless they exclude each other. Embodiments are depicted in thedrawings and are detailed in the description which follows.

FIG. 1 , which includes FIGS. 1A-1L, illustrates selected method stepsfor forming a semiconductor package with a plurality of conductivetracks and a metal pad on an upper surface of the encapsulant body,according to an embodiment.

FIG. 2 , which includes FIGS. 2A-2G, illustrates selected method stepsfor forming a semiconductor package with a plurality of conductivetracks and a metal pad on an upper surface of the encapsulant body,according to an embodiment.

DETAILED DESCRIPTION

Various embodiments of a method of forming a packaged semiconductordevice and a corresponding packaged semiconductor device are describedherein. The packaged semiconductor device is formed by mounting firstand second semiconductor dies on a die pad. The I/O terminals from thesecond semiconductor die are electrically connected to package leads byconductive tracks that are formed in an upper surface of the encapsulantbody. A load terminal from the second semiconductor die is connected toone or more of the package leads by a metal pad that is also formed inan upper surface of the encapsulant body. The conductive tracks providehigh density ad high performance electrical interconnect. Meanwhile, themetal pad provides a low electrical resistance connection, which may bea power connection such as a source or drain connection to a powertransistor die. Advantageously, the conductive tracks and the metal padcan be formed by metal structuring techniques at minimal expense.According to one embodiment, the encapsulant body of the package isformed to comprise a depression that exposes interior surface portionsof the leads, wherein thicker parts of the encapsulant body outside ofthe depression cover and retain the package leads. The conductive tracksand/or the metal pad can be directly formed and structured within thedepression. A protective structure such as a solder resist layer and/orlayer of thermal interface material may be arranged in the depressionover the conductive tracks and/or the metal pad.

Referring to FIG. 1 , a method of forming a packaged semiconductordevice comprises providing a die pad 100 and a plurality of leads 102.The die pad 100 and the plurality of leads 102 can each be provided by alead frame formed from metals such as copper (Cu), aluminum (Al), nickel(Ni), silver (Ag), palladium (Pd), gold (Au), etc., and alloys orcombinations thereof. The lead frame may be provided from asubstantially uniform thickness sheet of metal comprising any one orcombination of the above-listed metals and performing metal processingtechniques, e.g., stamping, etching, punching, etc., to form die pad 100and the plurality of leads 102. While the depicted embodiments show aso-called surface mount device configuration, the embodiments describedherein are more generally applicable to other types of packageconfigurations, including leadless packages (e.g., QFN) and through-holetype packages. The lead frame which provides the die pad 100 and theplurality of leads 102 may be part of a unit lead frame structurecomprising a peripheral ring or section (not shown) that is connected tothe leads 102 and die pad 100 prior to encapsulation.

A first semiconductor die 104 and a second semiconductor die 106 areprovided and are mounted on the die pad 100. The first and secondsemiconductor dies 104, 106 may be singulated from a semiconductor wafer(not shown), e.g. by sawing, prior to being mounting on the metal leadframe. In general, the semiconductor wafer and therefore the resultingsemiconductor die may be made of any semiconductor material suitable formanufacturing a semiconductor device. Examples of such materialsinclude, but are not limited to, elementary semiconductor materials suchas silicon (Si) or germanium (Ge), group IV compound semiconductormaterials such as silicon carbide (SiC) or silicon germanium (SiGe),binary, ternary or quaternary III-V semiconductor materials such asgallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP),indium phosphide (InP), indium gallium phosphide (InGaPa), aluminumgallium nitride (AlGaN), aluminum indium nitride (AlInN), indium galliumnitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indiumgallium arsenide phosphide (InGaAsP), etc.

Generally speaking, each of the first and second semiconductor dies 104,106 may have any device configuration. Examples of these deviceconfigurations include discrete device configurations, e.g., diodes,transistor, thyristors, etc., and integrated device configurations,e.g., logic devices, application specific integrated circuits (ASICs),ASSPs (application specific standard products), controllers, etc. Atleast one of the first and second semiconductor dies 104, 106 may bevertical devices, meaning that the device is configured to conductcurrent in a direction perpendicular to the main and rear surfaces ofthe respective semiconductor die. At least one of the first and secondsemiconductor dies 104, 106 may be a lateral device, meaning that thedevice is configured to conduct current in a direction parallel to amain surface of the respective semiconductor die.

The first and second semiconductor dies 104, 106 are each mounted on thedie pad 100. In the mounted position, the main surfaces of the first andsecond semiconductor dies 104, 106 face away from the die pad 100 andthe rear surfaces of the first and second semiconductor dies 104, 106face the die pad 100. An adhesive such solder, sinter, glue, etc., maybe provided between the rear surfaces of the first and secondsemiconductor dies 104, 106 and the die pad 100 to effectuate themounting. In the case of a vertical device, the adhesive may form aconductive connection between the rear surfaces of the first and secondsemiconductor dies 104, 106 and the die pad 100.

According to an embodiment, the first semiconductor die 104 comprises apower semiconductor device. Examples of power semiconductor devicesinclude power MISFETs (Metal Insulator Semiconductor Field EffectTransistors) power MOSFETs (Metal Oxide Semiconductor Field EffectTransistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs(Junction Gate Field Effect Transistors), HEMTs (High Electron MobilityTransistors), power bipolar transistors or power diodes such as, e.g.,PIN diodes or Schottky diodes, etc. In one particular embodiment, thefirst semiconductor die 104 comprises a vertical power transistor, e.g.,MOSFET IGBT, etc., that is rated to block voltages on the order of 100 V(volts), 600 V, 1200 V or more.

According to an embodiment, the second semiconductor die 106 comprises alogic device, Examples of logic device includes CMOS (complimentarymetal oxide semiconductor) based ASIC (application specific integratedcircuit) devices and ASSPs (application specific standard products). Inone particular embodiment, the second semiconductor die 106 comprises adriver circuit that is configured to control a switching operation thefirst semiconductor die 104, e.g., in the case that the firstsemiconductor die 104 comprises a power transistor.

The first semiconductor die 104 comprises a first load terminal 108disposed on the main surface of the first semiconductor die 104. Thefirst load terminal 108 may be a voltage blocking terminal of thedevice, e.g., source, drain, emitter, collector, etc. The firstsemiconductor die 104 comprises a second load terminal (not shown),which corresponds to an opposite voltage blocking terminal of thedevice, e.g., source, drain, emitter, collector, etc., from the firstload terminal. In the case of a vertical device configuration (asshown), the second load terminal may be disposed on a rear surface ofthe first semiconductor die 104, and may face and electrically connectwith the die pad 100, e.g., by a conductive adhesive such as solder orsinter. In this case, the die pad 100 is configured to provide a powersupply voltage to the first semiconductor die 104. In the case of alateral device configuration, the second load terminal of the firstsemiconductor die 104 may be disposed on the main surface of the firstsemiconductor die 104. The first semiconductor die 104 may furthercomprise one or more gate terminals 110 disposed on the main surface ofthe first semiconductor die 104, e.g., in the case of a transistordevice. In a commonly known manner, the gate terminal 110 may control aconductive connection between the first load terminal 108 and the secondload terminal of the first semiconductor die 104.

The second semiconductor die 106 comprises a plurality of I/O(input/output) terminals 112 disposed on a main surface of the secondsemiconductor die 106. The I/O terminals 112 refer to the terminals thatreceive or provide signals that modulate during operation, such asdigital logic signals. In the case that the second semiconductor die 106is a logic die, the I/O terminals 112 can comprise an input terminalthat receives an input signal for switching a semiconductor die, and anoutput terminal that is configured to provide a switching signal, e.g.,a PWM (pulse width modulation) to the gate terminal 110 of the secondsemiconductor die 106. The second semiconductor die 106 may additionallycomprise sensors, e.g., temperature sensors, short circuit sensors,etc., configured to monitor the operation of the first semiconductor die108 and to protect the first semiconductor die 108 in the event of ahazardous condition. The second semiconductor die 106 may additionallycomprise power supply terminals 114 that are disposed on the mainsurface of the second semiconductor die 106. The power supply terminals114 receive a fixed voltage such as a positive voltage and a referencepotential. Thus, in the case that the die pad 100 is configured toprovide a power supply voltage to the first semiconductor die 104, thesecond semiconductor die 106 can be powered independently via the powersupply terminals 114. In yet another embodiment, the secondsemiconductor die 106 may comprise a power semiconductor device, e.g., apower transistor, and a logic portion comprising driver circuitrymonolithically integrated therein. In that case, the power semiconductordevice of the second semiconductor die 106 may comprise a rear surfaceterminal that is electrically connected to the die pad 100 in a similarmanner as described above.

Referring to FIG. 1B, vertical interconnect elements 116 are formed onthe main surfaces of the first and second semiconductor dies 104, 106.The vertical interconnect elements 116 may be formed on any terminal,including the first load terminal 108 and the gate terminal 110 of thefirst semiconductor die 104, and the I/O terminals 112 and the powerterminals 114 of the second semiconductor die 106. The verticalinterconnect elements 116 are electrically conductive structures thatprovided an elevated point of electrical contact to the terminal towhich they are formed on. According to an embodiment, the verticalinterconnect elements 116 are configured as pillars, such ascopper-based pillars. According to another embodiment, the verticalinterconnect elements 116 are configured as stud bumps, such ascopper-based stud bumps, also possible to be vertical wires.

Referring to FIG. 1C, an encapsulant body 118 is formed on the leadframe structure. The encapsulant body 118 encapsulates the first andsecond semiconductor dies 104, 106, with the leads 102 protruding outfrom outer edge sides of the encapsulant body 118. According to anembodiment, the encapsulant body 118 is formed by a molding process suchas injection molding, transfer molding, compression molding, etc. someembodiments of the current invention is for leaded package, instead ofleadless package.

Generally speaking, the encapsulant body 118 can comprise anyelectrically insulating material that is suitable for semiconductorpackaging. Examples of these materials include mold compound, epoxy,thermosetting plastic, polymer, resin, fiber and glass woven fibermaterials, etc. According to an embodiment, the encapsulant body 118comprises a laser-activatable mold compound. A laser-activatable moldcompound refers to a mold compound that includes metal ions, e.g., Cu,Ni, Ag, etc. These metal ions are activated by a focused laser beamapplied to the mold compound, which creates an active metal at thesurface of the mold compound for a subsequent plating process, such aselectroless plating or electroplating technique. In addition to theadditive metal ions, a laser-activatable mold compound includes apolymer material as a base material. Examples of these polymers includethermoset polymers having a resin base, ABS (acrylonitrile butadienestyrene), PC/ABS (polycarbonate/acrylonitrile butadiene styrene), PC(polycarbonate), PA/PPA (polyimide/polyphthalamide), PBT (polybutyleneterephthalate), COP (cyclic olefin polymer), PPE (polyphenyl ether), LCP(liquid-crystal polymer), PEI (polyethylenimine or polyaziridine), PEEK(polyether ether ketone), PPS (polyphenylene sulfide), etc.

The encapsulant body 118 is formed such that upper ends of the of thevertical interconnect elements 116 are exposed at an upper surface 120of the encapsulant body 118 that is opposite from the die pad 100.Additionally, the encapsulant body 118 is formed such that interiorsurface portions 122 of the leads 102 are exposed at the upper surface120 of the encapsulant body 118. The interior surface portions 122 ofthe leads 102 refer to those surfaces of the leads 102 which extend toan inner end of the leads 102 which faces the die pad 100, and mayinclude an upper surface of the leads 102 that extends away from the diepad 100, and a side surface of the leads 102 that faces the die pad 100.This arrangement provides the benefit of making the later metal pad 134and/or conductive traces 130 easily connected to the respective dies andthe leads, and after the later step of applying protective structure 140on top of the encapsulant body 124, the metal pad 108 and the conductivetraces 130 are hidden and protected within the final semiconductorpackage.

According to the depicted embodiment, the encapsulant body 118 is formedto comprise a depression 124 in the upper surface 120 of the encapsulantbody 118. The depression 124 comprises first and second sidewalls 126,128 that are opposite from one another and a bottom surface 128 thatextends between the first and second sidewalls 126, 128. The exposedinterior surface portions 122 of the leads 102 may protrude out from oneor both of the first and second sidewalls 126, 128.

The depression 124 can be formed in a variety of different ways.According to one technique, the encapsulant body 118 is initially formedto have a substantially cubic shape and/or a substantially planar uppersurface 120, and the depression 124 is formed by subsequently removingthe encapsulant material from the upper surface 120 of the encapsulantbody 118, e.g., by polishing, grinding, etching, etc. According toanother technique, the depression 124 may be formed by appropriatelyconfiguring a mold tool cavity which forms the encapsulant body 118 toform the depression 124 as a molded feature. In either case, forming thedepression 124 in the upper surface 120 of the encapsulant body 118allows for the upper ends of the vertical interconnect elements 116and/or the interior surface portions 122 of the leads 102 to be exposedfrom the upper surface 120 of the encapsulant body 118. Meanwhile, theencapsulant body 118 comprises thicker portions 129 that are arrangedbetween the sidewalls 126 and the outer edge sides of the encapsulantbody 118. The leads 102 are anchored to the encapsulant body 118 by thethicker portions 129 and are electrically isolated from one another bythe thicker portions 129. This embodiment makes it is possible to makeleaded package, instead of leadless package.

Referring to FIG. 1D, a plurality of conductive tracks 130 are formed inthe upper surface 120 of the encapsulant body 118. The conductive tracks130 may be formed to directly contact the exposed interior surfaceportions 122 of the leads 102 and to directly contact the upper ends ofthe vertical interconnect elements 116. The plurality of conductivetracks 130 electrically connect at least some of the I/O terminals 112from the second semiconductor die 106 to a first group 132 of the leads102. The plurality of conductive tracks 130 may also electricallyconnect the power supply terminals 114 of the second semiconductor die106 to distinct ones of the leads 102 from the first group 132. Theconductive tracks 130 can therefore replace the need for other types ofinterconnect elements, such as bond wires, ribbons, clips, etc.

Additionally, a metal pad 134 is formed on the upper surface 120 of theencapsulant body 118. The metal pad 134 may be formed to directlycontact the exposed interior surface portions 122 of the leads 102 andto directly contact the upper ends of the vertical interconnect elements116. The metal pad 134 electrically connects the first load terminal 108of the first semiconductor die 104 to a second group 136 of the leads102, which comprises a number of leads that are not part of the firstgroup of the leads 102. That is, the metal pad 134 forms a separateelectrically conductive path between at least one of the leads 102 andthe first load terminal 108 of the first semiconductor die 104. Themetal pad 134 can therefore replace the need for other types ofinterconnect elements, such as bond wires, ribbons, clips, etc.

Due to its size, the metal pad 134 provides a low resistance connectionbetween the first load terminal 108 of the first semiconductor die 104and the leads 102. For instance, as shown, the metal pad 134 can beformed to occupy a large surface area, such as an area that coverssubstantially all of the first semiconductor die 104 and/or an areacompletely fills a region between the first and second sidewalls 126,128 of the depression 124. As a result, the interconnection has a largecurrent carrying capacity. Moreover, the arrangement of the metal pad134 in the depression 124 allows for the metal pad 134 make contact withmultiple ones of the leads 102 from the second group 136, thusdistributing a load current amongst multiple leads 102 and reducingelectrical resistance. Moreover, the large size of the metal pad 134allows the metal pad 134 to be used separately as an electrical contactstructure and/or a cooling structure that may be mated with an externalheat sink. Furthermore, having this large-size metal pad 134 eliminatesthe need of a clip which is commonly used in power semiconductorpackage, which is expensive and difficult to assemble.

According to an embodiment, the conductive tracks 130 and/or the metalpad 134 are formed by a laser direct structuring technique. According tothis technique, the encapsulant body 118 comprises a laser-activatablemold compound and a laser is applied to the upper surface 120 of theencapsulant body 118 at selected regions corresponding to the desiredlocation of the conductive tracks 130 and/or metal pad 134, as the casemay be. The applied laser energy creates laser activated regions in theencapsulant body 118, which forms complexes in the encapsulant body 118that act as a nuclei for a metal plating process. Subsequently, a metalplating process is performed so as to selectively deposit metal in thelaser activated regions without forming metal in adjacent locations ofthe encapsulant body 118 that do not comprise the complexes. This metalplating process may comprise an electroplating process, an electrolessplating process, or both. In either case, the device is submerged in achemical bath that contains metal ions (e.g., Cu+ ions, Ni+ ions, Ag+ions, etc.) that react with the organic metal complexes in the laseractivated regions, thereby forming the conductive tracks 130 and/ormetal pad 134, as the case may be.

According to another embodiment, the conductive tracks 130 and/or themetal pad 134 are formed by a laser assisted metal deposition technique.According to this technique, a metal powder is applied to the uppersurface 120 of the encapsulant body 118 at selected regionscorresponding to the desired location of the conductive tracks 130and/or metal pad 134, as the case may be. Subsequently, a laser beam isused to fuse the metal power together into a metal track and/or themetal pad 134 at the focal point of the laser beam.

According to another embodiment, the conductive tracks 130 and/or themetal pad 134 are formed by an ink jet metal printing process. Accordingto this technique, a viscous ink comprising a liquid solvent and aconductive metal, e.g., Ag, Cu, etc., is applied by a printer head inthe desired location and subsequently dried.

More generally, forming the conductive tracks 130 and the metal pad 134can comprise any one or more of: a laser direct structuring technique, alaser assisted metal deposition technique, an electroplating technique,and an electroless plating technique. The conductive tracks 130 may beformed by the same technique as the metal pad 134 or a differenttechnique as the metal pad 134. In the case that a laser directstructuring technique is not used to form either of the conductivetracks 130 and the metal pad 134, the encapsulant body 118 does not haveto comprise a laser-activatable mold compound.

Referring to FIGS. 1E-1H, alternate techniques for forming theelectrical interconnections between the terminals of the semiconductordies and the leads 102 are illustrated. The process steps shown in FIGS.1E-1H may be performed as an alternate way to form the interconnectelements 116 on the first semiconductor die 104. While FIGS. 1E-1H onlyshow the first semiconductor die 104, this technique may be incorporatedinto the previously described technique such that the steps for formingthe interconnect elements 116 on the second semiconductor die 106 mayremain the same.

According to the technique FIGS. 1E-1H, one or more ribbons 117 are usedto provide vertical electrical interconnect between the firstsemiconductor die 104 and the metal pad 134. In more detail, as shown inFIG. 1E, before forming the encapsulant body 118, at least one ribbon117 is bonded on the first terminal 108 of the first semiconductor die104 at multiple locations. Generally speaking, the continuous ribbon 117can be a an aluminum interconnect ribbon used in semiconductorpackaging, and can be bonded to the first semiconductor die 104 atmultiple locations, e.g., by a wedge bonding process. As shown from theplan-view perspective of the first semiconductor die 104, multiple onesof the ribbons 117 may be formed. Instead of the parallel linear patternas shown, other types of patterns, such as a crisscrossed patternswherein the ribbons 117 are disposed at perpendicular ornon-perpendicular angles relative to one another may be obtained. Asshown in FIG. 1F, the encapsulant body 118 is then formed, e.g.,according to the previously described techniques. As shown in FIG. 1F,the depression 124 is formed in the encapsulant body 118, e.g.,according to previously described techniques. In this case, thedepression 124 exposes apex points of the ribbons 117, thus creatingmultiple contact points for connecting to the first terminal 108 in asimilar manner as the interconnect elements 116 previously described. Asshown in FIG. 1F, the metal pad 134 is formed, e.g., according topreviously described techniques. The metal pad 134 is formed on theexposed apex points of the ribbons 117, thus forming an electricalconnection to the first load terminal 108.

Referring to FIGS. 1I and 1J, alternate techniques for forming theelectrical interconnections between the terminals of the semiconductordies and the leads 102 are illustrated. FIGS. 1I and 1J each illustratea process step that may be substituted for the process step shown inFIG. 1C.

Referring to FIG. 1I, the semiconductor package may be formed byperforming the same process steps as previously described with referenceto FIGS. 1A-1C, except that the vertical interconnect elements 116 havea different arrangement. Instead of being interspersed across an area ofthe first load terminal 108, e.g., as shown in FIG. 1B, in theembodiment of FIG. 1I, the vertical interconnect elements 116 on thefirst load terminal 108 are arranged only at the outer boundaries of thefirst load terminal 108, and more particularly at the corners of thefirst load terminal 108. Thus, when the encapsulant body 118 is formedas shown in FIG. 1I, the exposed vertical interconnect elements 116identify an outer boundary of the first load terminal 108. Statedanother way, the vertical interconnect elements 116 are arranged toprovide fiducial points indicating the location of the first loadterminal 108. With this arrangement, an opening may be formed in theencapsulant material that exposes at least part of or completely exposes(as shown in FIG. 1J) the first load terminal 108. The opening may beformed by a variety of different techniques, e.g., etching, lasering,etc. The vertical interconnect elements 116 on the first load terminal108 may optionally be removed at this time. After forming this opening,the metal pad 134 may be formed directly on the exposed part of thefirst load terminal 108. For instance, a plating technique such aselectroless plating or electroplating may be used, wherein the firstload terminal 108 of the first semiconductor die 104 acts as a seed forthis plating process. According to another technique, a separate metalstructure such as a flat metal plate may be arranged in the depression124 and directly attached and connected to the exposed first loadterminal 108 and the exposed surface portions of the second leads 102,e.g., by a soldering technique.

Referring to FIG. 1J, the semiconductor package may be formed byperforming the same process steps as previously described with referenceto FIGS. 1A-1C, except that no vertical interconnect elements 116 areused. In this case, the encapsulant body 118 is molded to compriseopenings 138 that expose the first load terminal 108 and the gateterminal 110 of the first semiconductor die 104, and the I/O terminals112 and the power terminals 114 of the second semiconductor die 106.This may be done by appropriately configuring a mold tool cavity that isused to form the encapsulant body 11. The conductive tracks 130 and themetal pad 134 may be formed on the device shown in FIG. 1J according tothe previously described techniques, e.g., laser direct structuring, alaser assisted metal deposition, electroplating, electroless plating,etc.

Referring to FIG. 1K, a protective structure 140 may be formed over theconductive tracks 130 after completing the metal structuring processes.The protective structure 140 may comprise an electrically insulatingmaterial. Thus, the protective structure 140 may cover and electricallyisolate the conductive tracks 130. For example, the electricallyinsulating protective structure 140 may comprise a solder resistmaterial such as a lacquer, epoxy, liquid photoimageable solder mask,dry-film photoimageable solder mask, etc. Meanwhile, the metal pad 134may remain exposed in the completed semiconductor package. In this way,the metal pad 134 can be electrically contacted and/or mated with heatsink in the completed semiconductor package. In that case, an optionalplating, such as an Sn plating may applied to the metal pad 134 forprotection/anticorrosion purposes.

Referring to FIG. 1L, an optional layer of thermally conductive material142 may be provided on the packaged semiconductor package. The layer ofthermally conductive material 142 can be provided over the metal pad 134and over the conductive tracks 130. In this case, the protectivestructure 140 may be omitted. The layer of thermally conductive material142 is an optional feature that may be provided if an electricalconnection to the metal pad 134 is not necessary. In that case, thelayer of thermally conductive material 142 in combination with the metalpad 134 provide a heat dissipation feature that can extract heat fromthe first and second semiconductor dies 104, 106 during operation. Aheat sink may be attached to the layer of thermally conductive material142, wherein the electrically insulating properties of the layer ofthermally conductive material 142 provide electrical isolation.

Referring to FIG. 2 , a method of forming a packaged semiconductordevice is depicted, according to an embodiment. According to the of FIG.2 , the packaged semiconductor device comprises a stacked arrangement ofmultiple semiconductor dies, and the metal structuring techniquedescribed above is used to form the interconnections from thesemiconductor dies to the package leads and between the stackedsemiconductor dies.

As shown in FIG. 2A, a lead frame comprising the die pad 100 and theplurality of leads 102 is provided. A first semiconductor die 144 ismounted on the die pad 100. According to an embodiment, the firstsemiconductor die 144 comprises a power transistor device block and alogic block monolithically integrated in the first semiconductor die144. More particularly, the first semiconductor die 144 may comprise apower transistor, e.g., MOSFET, IGBT, etc. incorporated into a firstpart of the first semiconductor die 144, and logic circuitry that isconfigured to control a switching operation the power transistorincorporated into a second, different part of the first semiconductordie 144. Thus, the first semiconductor die 144 may combine the circuitryof the first and second semiconductor dies 104, 106 from the embodimentdescribed with reference to FIG. 1 . Accordingly, the firstsemiconductor die 144 may comprise a first load terminal 108 and aplurality of I/O terminals 112 disposed on a main surface of the firstsemiconductor die 144, and a second load terminal (not shown) disposedon a rear surface of the first semiconductor die 144, wherein theseterminals perform the same function as the correspondingly identifiedterminals as described in FIG. 1 .

Referring to FIG. 2B, a second semiconductor die 146 is mounted on thefirst semiconductor die 144. The second semiconductor die 146 may be avertical device, with a first load terminal 108 disposed on a mainsurface of the second semiconductor die 146 and a second load terminal(not shown) disposed on a rear surface of the second semiconductor die146. The second semiconductor die 146 may be substantially similar oridentical to the first semiconductor die 104 described with reference toFIG. 1 . Accordingly, the second semiconductor die 146 may be configuredas a discrete vertical transistor device, e.g., MOSET, IGBT, etc., andthus may further comprise a gate terminal 110. In one particularembodiment, the second semiconductor die 146 comprises a vertical powertransistor, e.g., MOSFET IGBT, etc., that is rated to block voltages onthe order of 100 V (volts), 600 V, 1200 V or more.

As shown, the second semiconductor die 146 may be mounted directly onthe first load terminal 108 of the first semiconductor die 144. Thus,the second load terminal (not shown) of the second semiconductor die 146may face and electrically connect with the first load terminal 108 ofthe first semiconductor die 144. A conductive adhesive, e.g., solder,sinter, etc. may be used to effectuate this connection.

According to an embodiment, the stacked arrangement of the firstsemiconductor die 144 and the second semiconductor die 146 is arrangedto form a half-bridge circuit. A half-bridge circuit refers to one typeof circuit topology that is used in a power conversion circuit, such asa DC to DC converter, DC to AC converter, etc. A half-bridge circuitcomprises a high-side switch connected in series with a low-side switch.One load terminal of the high-side switch (e.g., the drain) is connectedto a first DC voltage (e.g., a positive potential), one load terminal ofthe low-side switch (e.g., the source) is connected to a second DCvoltage (e.g., negative potential or ground), and the remaining two loadterminals (e.g., the source of the high-side switch and the drain of thelow-side switch) are connected together to form the output of thehalf-bridge circuit. The control terminals of the high-side and low-sideswitch (e.g., the gate terminals) can be switched according to a powercontrol scheme (e.g., pulse width modulation) to produce a desiredvoltage and frequency at the output of the half-bridge circuit.

The second semiconductor die 146 may provide the high-side switch of thehalf-bridge circuit, the power transistor incorporated into the powertransistor device block of the first semiconductor die 144 may providethe low-side switch of the half-bridge circuit, and the logic circuitincorporated into the logic block of the second semiconductor die 146may provide the driver circuit of the half-bridge circuit.

As shown, the packaged semiconductor may additionally comprise a thirdsemiconductor die 148 mounted on the die pad 100 and a fourthsemiconductor die 150 mounted on top of the third semiconductor die 148.The third and fourth semiconductor dies 148, 150 may have the sameconfiguration as the first and second semiconductor dies 144, 146 thatare mounted in a stacked arrangement on the same the die pad 100. Thus,third semiconductor die 148 may comprise power transistor device blockand a logic block monolithically integrated in third semiconductor die148, and the fourth semiconductor die 150 may be configured as adiscrete vertical transistor. Moreover, the stacked arrangement of thethird semiconductor die 148 and the fourth semiconductor die 150 may bearranged to form a second half-bridge circuit. Thus, a full-bridgecircuit may be realized. More generally, the stacking concept may beused to provide different types of multi-phase circuits, e.g., threephase circuits.

Referring to FIG. 2C, the vertical interconnect elements 116 are formedon terminals of the semiconductor dies. As shown, the verticalinterconnect elements 116 are formed on the I/O terminals 112 of thefirst and third semiconductor dies 144, 148, the power terminals 114 ofthe first and third semiconductor dies 144, 148, and the gate terminals110 of the second and fourth semiconductor dies 146, 148. Moregenerally, the vertical interconnect elements 116 can be formed on anyupper surface terminals of the first, second, third and fourthsemiconductor dies 144, 146, 148, 150.

Referring to FIG. 2D, the encapsulant body 118 is formed. The verticalinterconnect elements 116 are exposed a similar manner as previouslydescribed with reference to FIG. 1C. Different to the encapsulant body118 shown in FIG. 1C, the encapsulant body 118 of FIG. 2C comprises atwo-tiered depression 124, with a lower tier 152 of the depression 124being disposed over the non-overlapping portions of the first and thirdsemiconductor dies 144, 148, and an a upper tier 154 of the depression124 being disposed over the second and fourth semiconductor dies 146,150. In this way, the vertical interconnect elements 116 at differentvertical levels can be accessed.

Referring to FIG. 2E, openings 138 are formed in the encapsulant body118. In this case, the openings are formed to expose the first loadterminals 108 of the first, second, third and fourth semiconductor dies144, 146, 148, 150. The openings 138 may be formed by techniques such aslasering, etching, etc. Prior to forming the openings 138, depressionsmay be formed over each of the first load terminals 108 of the first,second, third and fourth semiconductor dies 144, 146, 148, 150.According to an embodiment, the mold cavity which forms the encapsulantbody 118 is configured to create these depressions, thus minimizing theamount of encapsulant material to be removed.

Referring to FIG. 2F, a plurality of conductive tracks 130 and metalpads 134 are formed in the encapsulant body 118. The conductive tracks130 and the metal pads 134 may be formed according to any of thepreviously described techniques. The conductive tracks 130 electricallyconnect the I/O terminals 112 and the power terminals 114 of the firstsemiconductor die 144 with a first group 156 of the leads, andelectrically connect the I/O terminals 112 and the power terminals 114of the third semiconductor die 148 with a second group 158 of the leads.Moreover, the conductive tracks 130 electrically connect the I/Oterminals 112 of the first semiconductor die 144 with gate terminals 110of the second semiconductor die 146, and electrically connect the I/Oterminals 112 of the third semiconductor die 148 with gate terminals 110of the fourth semiconductor die 150. Meanwhile, a first one of the metalpads 134 electrically connects the first load terminal 108 of the secondsemiconductor die 146 to a third group 160 of the leads 102, a secondone of the metal pads 134 electrically connects the first load terminal108 of the first semiconductor die 144 to a fourth group 162 of theleads 102, a third one of the metal pads 134 electrically connects thefirst load terminal 108 of the fourth semiconductor die 150 to a fifthgroup 164 of the leads 102, and a fourth one of the metal pads 134electrically connects the first load terminal 108 of the thirdsemiconductor die 148 to a sixth group 166 of the leads 102. In the caseof a half-bridge circuit configuration, the first and third groups 160,164 of the leads 102 can provide a fixed voltage supply to the high-sideswitches, the die pad 110 can provide a fixed voltage supply to the lowside switches, and the second and fourth groups 162, 166 of the leads102 can form the output terminals.

Referring to FIG. 2G, an optional layer of thermally conductive material142 may be provided on the packaged semiconductor package. The layer ofthermally conductive material 142 can be provided over the metal pads134 and over the conductive tracks 130 in a similar manner as previouslydescribed.

The term “electrically connected” as used herein describes a permanentlow-ohmic, i.e., low-resistance, connection between electricallyconnected elements, for example a wire connection between the concernedelements. Two elements may electrically connected by to one another bydirect physical contact between the elements or by an electricallyconductive intermediary, such as a wire, solder, contact pad, etc.,provided between the elements.

Spatially relative terms such as “under,” “below,” “lower,” “over,”“upper” and the like, are used for ease of description to explain thepositioning of one element relative to a second element. These terms areintended to encompass different orientations of the device in additionto different orientations than those depicted in the figures. Further,terms such as “first,” “second,” and the like, are also used to describevarious elements, regions, sections, etc. and are also not intended tobe limiting. Like terms refer to like elements throughout thedescription.

As used herein, the terms “having,” “containing,” “including,”“comprising” and the like are open-ended terms that indicate thepresence of stated elements or features, but do not preclude additionalelements or features. The articles “a,” “an” and “the” are intended toinclude the plural as well as the singular, unless the context clearlyindicates otherwise.

It is to be understood that the features of the various embodimentsdescribed herein may be combined with each other, unless specificallynoted otherwise.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A method of forming a packaged semiconductordevice, the method comprising: providing a lead frame comprising a diepad and a plurality of leads; providing a first semiconductor die thatcomprises a first load terminal disposed on a main surface of the firstsemiconductor die; providing a second semiconductor die that comprises aplurality of I/O terminals disposed on a main surface of the secondsemiconductor die, mounting the first and second semiconductor dies onthe lead frame such that the main surfaces of the first and secondsemiconductor dies each face away from the die pad; forming anencapsulant body of electrically insulating mold compound thatencapsulates the first and second semiconductor dies; forming aplurality of conductive tracks on an upper surface of the encapsulantbody that electrically connect at least some of the I/O terminals fromthe second semiconductor die to a first group of the leads; and forminga metal pad on the upper surface of the encapsulant body thatelectrically connects the first load terminal to a second lead.
 2. Themethod of claim 1, wherein the encapsulant body is formed to exposeinterior surface portions of the leads at the upper surface of theencapsulant body, wherein the conductive tracks are formed to contactthe interior surface portions of the leads from the first group of theleads, and wherein the metal pad is formed to contact the interiorsurface portion of the second lead.
 3. The method of claim 2, whereinthe encapsulant body is formed to comprise a depression in the uppersurface of the encapsulant body, and wherein the exposed interiorsurface portions of the leads protrude out from a first sidewall of thedepression.
 4. The method of claim 2, further comprising formingvertical interconnect elements on the I/O terminals of the secondsemiconductor die before forming the encapsulant body, wherein theencapsulant body is formed to expose upper ends of the verticalinterconnect elements that are disposed on the I/O terminals at theupper surface of the encapsulant body, and wherein the conductive tracksare formed to contact the exposed upper ends of the verticalinterconnect elements that are disposed on the I/O terminals.
 5. Themethod of claim 2, wherein forming either one of the plurality ofconductive tracks and the metal pad comprises any one or more of: laserassisted metal deposition; inkjet metal printing; electroplating; andelectroless plating.
 6. The method of claim 2, further comprisingforming vertical interconnect elements on the first load terminal of thefirst semiconductor die before forming encapsulant body, and wherein theencapsulant body is formed to expose upper ends of the verticalinterconnect elements on the first load terminal at the upper surface ofthe encapsulant body.
 7. The method of claim 6, wherein the metal pad isformed on the upper surface of the encapsulant body so as to contact theexposed upper ends of the vertical interconnect elements on the firstload terminal.
 8. The method of claim 6, further comprising forming anopening in the upper surface of the encapsulant body that exposes thefirst load terminal of the first semiconductor die, and wherein formingthe opening comprises using the exposed upper ends of the verticalinterconnect elements on the first load terminal to identify a locationof the first load terminal underneath the encapsulant body.
 9. Themethod of claim 2, further comprising forming a ribbon on the first loadterminal of the first semiconductor die before forming encapsulant body,wherein the encapsulant body is formed to expose apex points of theribbon at the upper surface of the encapsulant body, and wherein themetal pad is formed on the exposed apex points of the ribbon.
 10. Themethod of claim 2, further comprising forming a solder mask over theconductive tracks.
 11. The method of claim 2, further comprising forminga layer of electrically insulating and thermally conductive materialthat covers the metal pad.
 12. The method of claim 1, wherein theencapsulant body is formed to directly expose the first load terminaland the I/O terminals at the first surface of the encapsulant body. 13.The method of claim 1, wherein the first semiconductor die is a powertransistor die that comprises a gate terminal disposed on the mainsurface of the first semiconductor die, wherein the second semiconductordie is a logic die, and wherein the method further comprises: forming asecond conductive track on the upper surface of the encapsulant bodythat electrically connects one of the I/O terminals from the secondsemiconductor die to the gate terminal of the first semiconductor die.14. The method of claim 13, wherein the first semiconductor diecomprises a second load terminal that is disposed on a rear surface ofthe first semiconductor die, wherein the second load terminal of thefirst semiconductor die faces and electrically connects with the diepad.
 15. A method of forming a packaged semiconductor device, the methodcomprising: providing a lead frame comprising a die pad and a pluralityof leads; providing a first semiconductor die that comprises a firstload terminal and a plurality of I/O terminals disposed on a mainsurface of the first semiconductor die; providing a second semiconductordie that comprises a first load terminal and a gate terminal disposed ona main surface of the second semiconductor die; mounting the firstsemiconductor die directly on the lead frame such that the main surfaceof the first semiconductor die faces away from the lead frame; mountingthe second semiconductor die on the first semiconductor die such thatthe main surface of the second semiconductor die faces away from thelead frame; forming an encapsulant body of electrically insulating moldcompound that encapsulates the first and second semiconductor dies;forming a plurality of first conductive tracks on an upper surface ofthe encapsulant body that electrically connect at least some of the I/Oterminals from the first semiconductor die to a first group of theleads; forming a second conductive track on the upper surface of theencapsulant body that electrically connects one of the I/O terminalsfrom the first semiconductor die to the gate terminal of the secondsemiconductor die; forming a first metal pad on the upper surface of theencapsulant body that electrically connects the first load terminal ofthe first semiconductor die to a second lead; and forming a second metalpad on the upper surface of the encapsulant body that electricallyconnects the first load terminal of the second semiconductor die to athird lead.
 16. The method of claim 15, wherein the first semiconductordie comprises a power transistor device block and a logic blockmonolithically integrated in the first semiconductor die, wherein thesecond transistor die comprises a power transistor device, wherein thepower transistor device block of the first semiconductor die and thepower transistor device of the second semiconductor die form ahalf-bridge circuit, and wherein the logic block of the firstsemiconductor die forms a driver circuit that is configured to control aswitching operation of the half-bridge circuit.
 17. The method of claim16, further comprising: providing a third semiconductor die thatcomprises a first load terminal and a plurality of I/O terminalsdisposed on a main surface of the third semiconductor die; providing afourth semiconductor die that comprises a first load terminal and a gateterminal disposed on a main surface of the fourth semiconductor die;mounting the third semiconductor die directly on the lead frame suchthat the main surface of the third semiconductor die faces away from thelead frame; and mounting the fourth semiconductor die on the thirdsemiconductor die such that the main surface of the fourth semiconductordie faces away from the lead frame; wherein the third semiconductor diecomprises a power transistor device block and a logic blockmonolithically integrated in the third semiconductor die, wherein thefourth transistor die comprises a power transistor device, wherein thepower transistor device block of the third semiconductor die and thepower transistor device of the fourth semiconductor die form a secondhalf-bridge circuit, and wherein the logic block of the thirdsemiconductor die forms a driver circuit that is configured to control aswitching operation of the second half-bridge circuit.
 18. A packagedsemiconductor device, comprising: a lead frame comprising a die pad anda plurality of leads; a first semiconductor die that comprises a firstload terminal disposed on a main surface of the first semiconductor diethat faces away from the die pad; a second semiconductor die thatcomprises a plurality of I/O terminals disposed on a main surface of thesecond semiconductor die that faces away from the die pad; anencapsulant body of electrically insulating mold compound thatencapsulates the first and second semiconductor dies; a plurality ofconductive tracks that are formed on an upper surface of the encapsulantbody and electrically connect at least some of the I/O terminals fromthe second semiconductor die to a first group the leads; and a metal padformed on the upper surface of the encapsulant body that electricallyconnects the first load terminal to a second lead.
 19. The packagedsemiconductor device of claim 18, wherein interior surface portions ofthe leads are exposed at the upper surface of the encapsulant body, andwherein the metal pad and the conductive tracks contact the exposedinterior surface portions of the leads.
 20. The packaged semiconductordevice of claim 19, wherein the encapsulant body comprises a depressionin the upper surface of the encapsulant body, and wherein the exposedinterior surface portions of the leads protrude out from a first outersidewall of the depression.
 21. The packaged semiconductor device ofclaim 20, wherein the depression is spaced apart from an outer edge sideof the encapsulant body by a thicker portion of the of the encapsulantbody, and wherein upper surfaces of the leads are covered by encapsulantmaterial in the thicker portion.
 22. The packaged semiconductor deviceof claim 21, wherein the depression comprises a second sidewall that isopposite from the first sidewall and a bottom surface, and wherein themetal pad completely fills a region between the first and secondsidewalls of the depression.
 23. The packaged semiconductor device ofclaim 18, wherein the first semiconductor die is a power transistor diethat comprises a gate terminal disposed on the main surface of the firstsemiconductor die, wherein the second semiconductor die is a logic die,and wherein the semiconductor package further comprises a secondplurality of conductive tracks on the upper surface of the encapsulantbody that electrically connect at least one of the I/O terminals fromthe second semiconductor die to the gate terminal of the secondsemiconductor die.
 24. The packaged semiconductor device of claim 18,wherein the first semiconductor die is mounted on top of the secondsemiconductor die, and wherein the second semiconductor die is mounteddirectly on the die pad.